With increases in the scale of systems in recent years, there has been an increase in the capacity of mounted memory, and high reliability is also sought. Prompt detection of the location of malfunctions in memory is essential for maintaining high reliability of large amounts of memory. To this end, memory diagnostics and monitoring are indispensable.
FIG. 1 explains memory monitoring in the prior art. An operating system (hereafter “OS”) is running in the CPU 3. The CPU 3 is connected to memory units 2i to 2l. 
In memory anomaly monitoring of the prior art the CPU monitors all memory areas in the memory units 2i to 2l in response to instructions from the OS. In this case, read processing is performed by the OS via the CPU 3 of all areas in the mounted memory units 2i to 2l. An area from which reading is not possible is diagnosed as an error area, and degradation processing to remove the error area from the usable area is performed.
The OS holds information on areas which the OS has itself an information of degraded area, and itself secures the continuity of logical addresses. Further, the OS ascertains in advance the mounted memory capacity and hardware configuration.
In such a method in which the CPU monitors all memory areas under instruction from the OS, the load occurring at the time of operation is excessive in a large-scale system which a huge memory capacity. Moreover, there is the problem that too much time is required for monitoring processing. In order to alleviate the load on the CPU, memory monitoring in which hardware other than the CPU performs reading of memory areas is conceivable. By having hardware other than the CPU read memory areas and confirm the presence or absence of errors in the read-out data, the load on the CPU can be alleviated.
FIG. 2 is an example of memory monitoring performed by hardware other than the CPU. The OS is running in the CPU 3. And, controllers C1 to C3, which are the hardware performing control and monitor of memory, are connected to the CPU 3. Controller C1 is connected to memory units 2m and 2n, controller C2 is connected to memory units 2o and 2p, and controller C3 is connected to memory units 2q and 2r. 
The controller C1 to C3 control access to connected memory units according to requests from the OS during normal access, but during memory monitoring perform data reading from memory units, and upon detecting an error change specific bits in a register of the controller and notify the OS.
In this case also, the OS has ascertained in advance the amount of memory mounted and the hardware configuration. Further, the OS itself holds information on previously degraded areas, and itself secures the continuity of logical addresses.
The technology described in Japanese Patent Laid-open No. 2000-57016 is a hardware monitoring system which alleviates the load on the CPU. This technology suppresses frequent interruptions of applications due to errors and reduces the load on the CPU by causing error processing to be performed by firmware. However, the technology of Japanese Patent Laid-open No. 2000-57016 relates to hardware in general, and does not perform monitoring of memory.
As shown in FIG. 2, even when hardware other than the CPU is used to perform memory anomaly monitoring, there is the possibility that memory addresses may be changed from the addresses of the previous architecture due to memory expansion. In order to accommodate memory expansion, conversion into logical addresses corresponding to each architecture must be performed; if the OS is caused to execute this conversion, however, not all architectures can be accommodated by a common OS. Moreover, if measures are taken to accommodate changes in architecture due to hardware, then the need arises to install additional hardware for each architecture, resulting in cost increases and increases in development processes.